CF112P Description

The CF112P is an extremely low additive jitter 1:2 LVPECL clock fanout and divider. Its sensitive differential input receiver accepts low amplitude sinewave, CMOS, LVPECL, LVDS, CML, and HCSL signals to perform LVPECL output logic level translation, signal fanout, and configurable frequency division (or passthrough) up to 1000MHz. The CF112P is designed to meet extremely low additive jitter and skew requirements operating in an extended temperature range. The divide functionality (or passthrough) is configured with static voltages to external control pins.

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Block Diagram

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  • Input signal sensitivity down to 30mVpp
  • Input/output signal frequency up to 1000MHz
  • Additive Jitter <20fs @ 1GHz, <40fs @ 156MHz
  • 30ps output to output skew
  • Configurable output divider
  • Extended Temp Range: -55°C to 125°C


  • 5G/6G clock distribution
  • Low jitter clock trees
  • Logic translation & signal restoration
  • Wired & Wireless communications
  • Microprocessor clock distribution
  • High speed ADC, DAC clock driver

Order Numbers

Order NumberPackageQuantity / FormRoHSMSL RatingLeadframe
CF112P-T116L TSLP QFN123 / TubeYes1NiPdAu
CF112P-R116L TSLP QFN1000 / 7" ReelYes1NiPdAu