ASIC Design Flow
Hexius Semiconductor’s ASIC design flow is a proven process developed with our engineer’s experience of many design cycles. Our ASIC design flow applies to all project sizes and supports fully customized designs that meet all design requirements with low risk.
The first step to any successful ASIC design is for all parties to initially discuss the ASIC’s requirements, technical challenges, economics and schedule to determine if a partnership between Hexius Semiconductor and our customer is feasible. Hexius Semiconductor treats our customer’s ASIC developments as a partnership that requires both parties to tightly engage in the project which greatly increases the project’s success. Once the scope of the project is understood and defined, Hexius Semiconductor will generate an extensive ASIC development contract, free of charge, that includes the following:
- •Initial specifications, block diagrams and pinouts
- •Proposed implementation (architectures, foundry process)
- •Define target die size
- •Legal framework
Once all parties sign off and agree to the ASIC proposal, Design Phase 1 starts and begins to build the crucial foundation for the development of the ASIC. To facilitate and build the partnership relationships, the appropriate Hexius Semiconductor engineers and management prefer to travel to our customer’s facility to personally meet the individuals they will work with throughout the design cycle and discuss in detail the finer aspects and specifications of the ASIC. Design Phase 1 completes the following:
- •Project definition and ASIC specification agreement
- •System architecture and top level schematics
- •Establish testing requirements
- •Define packaging requirements
- •Define external interfacing
- •High level modeled simulations
The completion of Design Phase 1 results in the first of 3 major design reviews where Hexius Semiconductor will draft a design review document that will be provided to all parties. Upon customer approval, the ASIC moves into the next design phase.
After specifications, modeling and architectures are known, the design flow moves towards block level design. In this phase, Hexius Semiconductor will custom build all of the ASIC’s block level transistor schematics and layouts. This represents the bulk of the work regarding the ASIC’s development as the circuit schematics are also thoroughly simulated and refined to make sure they meet their performance specifications. If practical, Hexius Semiconductor will also incorporate design critical blocks on prototype wafer runs to reduce risk and provide real silicon data before the complete design is sent to the foundry. Design Phase 2 completes the following:
- •Defines all ASIC block specifications
- •Transistor and logic level schematic design for ASIC analog circuit blocks
- •Comprehensive performance simulation verification (process, voltage, temperature range, Monte Carlo)
- •Layout design for ASIC circuit blocks
- •Extracted layout parasitic simulations verification
- •Completed verilog coding and synthesis
- •Initial digital circuitry place and route and timing checks
- •Complete Design Rule Checks (DRC) and Layout Vs. Schematic (LVS) verification
- •Top level floorplanning and final pad/pin locations
The completion of Design Phase 2 results in the second of 3 major design reviews where Hexius Semiconductor will draft a design review document that will be provided to all parties. Due to the large amount of information that results from this design phase, an interim design review is often necessary midway through this phase. Upon customer approval, the ASIC moves into the next design phase.
The last of the design phases of the ASIC’s development focuses on the final integration of the design and performing all the necessary function and performance compliance to complete the database. Once complete, the ASIC’s physical design has concluded and is ready to be released to the foundry for fabrication. Design Phase 3 completes the following:
- •Top Level mixed-signal circuit integration
- •Functional simulations to verify top level operation (Mixed-signal/analog/digital simulations as appropriate)
- •Comprehensive performance simulations to verify specification compliance
- •Final tuning of block level circuits
- •Top level ASIC layout completion
The completion of Design Phase 3 results in the final of 3 major design reviews where Hexius Semiconductor will draft a design review document that will be provided to all parties. Upon customer approval, the ASIC moves into mask generation and engineering (prototype) wafers.
After the completion of Design Phase 3, a GDS database is delivered to the wafer foundry to construct the wafers masks. Wafer masks generally consist of 20-30 plates (Single layer masks, or SLM) and are used to construct the individual process layers during wafer production but when building engineering (prototype) wafers, this number can be reduced by half to save costs (multi-layer masks, or MLM). MLM masks are usually not used for full production volumes but rather engineering wafer lot quantities consisting between 3 to 12 wafers and are utilized to evaluate and characterize the ASIC before moving into production. Using MLM and engineering wafers provides Hexius Semiconductor and our customer opportunities to evaluate, adjust and sample the design based on lab test results at a lower cost and more efficient timeline.
Hexius Semiconductor will receive the engineering wafers from the foundry and usually process the wafer into individual packages to evaluate the ASIC design. The alternative is too evaluate the design as bare die which can also be accomplished in parallel with packaging. The packaged parts are then initially evaluated in our lab for correct operation and then sent to the customer for their own evaluation. Hexius Semiconductor and our customers then work together in fully evaluating and characterizing the design to verify the performance, discover any abnormalities or prove out any adjustments that need to be implemented. As our customers are experts in their engineering field, they generally focus on evaluating the ASIC design within their system while Hexius Semiconductor focuses on evaluating the performance of the specific ASIC. The parallel evaluation is a highly interactive cooperation that thoroughly vets the ASIC.
The final stage in the ASIC design flow is the test development and full scale production. Test development actually occurs throughout the Design Phase 1,2 and 3 as Hexius Semiconductor plans on what to test and how to test it when we design the schematics and access points but only after the ASIC’s characterization is the full test requirement understood. Our ASICs also include built in self test features as much as possible.
The timeline for production is set by our customers and their understanding of the market for their products. Once the decision is made to go to full production, Hexius Semiconductor can easily scale the manufacturing to the desired level. In some low production volume scenarios, the engineering wafers may even be sufficient for production. Throughout the production lifetime of the ASIC, Hexius Semiconductor will support the design, manufacturing, testing and quality of the design. All finished goods are inventoried and sold out of Hexius Semiconductor facilities.
Contact us for additional information!