CF128C Description

The CF128C is an extremely low additive jitter 2:8 CMOS clock fanout and divider. Its sensitive differential input receiver accepts low amplitude sinewave, CMOS, LVPECL, LVDS, CML, and HCSL signals to perform CMOS output logic level translation, signal fanout, and configurable frequency division (or passthrough) up to 200MHz. The CF128C is designed to meet extremely low additive jitter and skew requirements operating in an extended temperature range. The divide functionality (or passthrough) is configured with static voltages to external control pins.

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Block Diagram

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  • Input signal sensitivity down to 30mVpp
  • Input/output signal frequency up to 200MHz
  • Additive Jitter <35fs @ 38.4MHz
  • 30ps output to output skew
  • Configurable output divider
  • Extended Temp Range: -55°C to 125°C


  • 5G/6G clock distribution
  • Low jitter clock trees
  • Logic translation & signal restoration
  • Wired & Wireless communications
  • Microprocessor clock distribution
  • Clock driver

Order Numbers

Order NumberPackageQuantity / FormRoHSMSL RatingLeadframe
CF128C-T120L UTSLP QFN120 / TubeYes1NiPdAu
CF128C-R120L UTSLP QFN1000 / 7" ReelYes1NiPdAu