CF124P Description

The CF124P is an extremely low additive jitter 2:4 LVPECL MUX clock fanout and divider. It accepts sinewave, CMOS, LVPECL, LVDS, CML, and HCSL signals to perform LVPECL output logic level translation, signal fanout, and programmable frequency division (or passthrough) from 1MHz to 1000MHz. The CF124P is designed to meet extremely low additive jitter and skew requirements operating in an extended temperature range. The divide functionality (or passthrough) is configured with static voltages to external control pins. The CF124P is enclosed in a 4mm x 4mm package.

Block Diagram

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  • Input signal sensitivity down to 30mVpp
  • Input/output signal frequency up to 1000MHz
  • Additive Jitter <20fs @ 1GHz, <40fs @ 156MHz
  • 30ps output to output skew
  • Configurable output divider
  • Extended Temp Range: -55°C to 125°C


  • 5G/6G clock distribution
  • Low jitter clock trees
  • Logic translation & signal restoration
  • Wired & Wireless communications
  • Microprocessor clock distribution
  • High speed ADC, DAC clock driver

Documents & Downloads


Order Numbers

Order NumberPackageQuantity / FormRoHSMSL RatingLeadframe
CF124P-CT124L TSLP QFNTBD / TubeYes1NiPdAu
CF124P-CR124L TSLP QFN1000 / 7" ReelYes1NiPdAu