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[one_half last=”no” class=”” id=””]Description

The CF1216 is a ludicrously low additive jitter 1:6 LVPECL clock fanout and divider. It is capable of receiving CMOS, LVPECL, LVDS, CML and HCSL input levels, LVPECL output logic level translation and programmable frequency division. The CF1216 is programmed through external control pins and is enclosed in a 4mm x 4mm MLP package.

Recommended for new designs [/one_half] [one_half last=”yes” class=”” id=””]Block Diagram

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  • • 1000MHz maximum output frequency
  • • Sub 40fs additive jitter
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  • • Programmable output divider
  • • 1, 2, 4, 8, 16, 32 divide ratios
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  • • 2.5 – 3.3V analog supply
  • • Extended Temp Range: -55°C to 125°C
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 Datasheet Brief – coming soon


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  • • General purpose clock distribution
  • • Low jitter clock trees
  • • Logic translation & signal restoration
  • • Wired & Wireless communications
  • • Microprocessor clock distribution
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Order Numbers

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