Clock Fanout Buffers & Translators

Hexius Semiconductor’s configurable clock fanout buffers & translators are the best solution for distributing low phase noise clock signals with the absolute minimum amount of additive clock jitter. In addition to ludicrously low additive jitter performance, our clock fanout products accept a wide range of input levels, configurable input biasing and programmable divide ratios.

Resources

  • Application Guide
Part Number Input Termination Input Channels Output Channels Output Level Max Frequency
CF1112 No 1 2 CMOS 200MHz
CF1114 No 1 4 CMOS 200MHz
CF1116 No 1 6 CMOS 200MHz
CF1118 No 1 8 CMOS 200MHz
CF1124 No 2 4 CMOS 200MHz
CF1126 No 2 6 CMOS 200MHz
CF1128 No 2 8 CMOS 200MHz
CF1212 No 1 2 LVPECL 1000MHz
CF1214 No 1 4 LVPECL 1000MHz
CF1216 No 1 6 LVPECL 1000MHz
CF1218 No 1 8 LVPECL 1000MHz
CF1224 No 2 4 LVPECL 1000MHz
CF1228 No 2 8 LVPECL 1000MHz
CF1132 Yes 1 2 CMOS 200MHz
CF1134 Yes 1 4 CMOS 200MHz
CF1136 Yes 1 6 CMOS 200MHz
CF1138 Yes 1 8 CMOS 200MHz
CF1232 Yes 1 2 LVPECL 1000MHz
CF1234 Yes 1 4 LVPECL 1000MHz
CF1236 Yes 1 6 LVPECL 1000MHz
CF1238 Yes 1 8 LVPECL 1000MHz